LLNN: A Scalable LUT-Based Logic Neural Network Architecture for FPGAs

When deploying neural networks for inference on specialized hardware devices such as field-programmable gate arrays (FPGAs), designers often face challenges due to limited on-chip memory. Techniques like pruning and quantization reduce network size but often lead to suboptimal designs when transitioning from software frameworks to hardware implementations. A co-design approach using Logic Neural Networks (LNNs) offers an alternative that takes hardware characteristics into account from the outset, replacing conventional neurons with logic gates. However, this approach introduces scalability issues for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i>-input Boolean functions, with parameter complexity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathcal {O}(2^{2^{k}})$</tex-math> </inline-formula> and high routing overhead, making FPGA implementation both complex and time-consuming. To address these limitations, we propose a novel look-up table (LUT) logic neural network architecture (LLNN), where each neuron is implemented as a LUT encoding a logic function. This architecture leverages the LUT-rich structure of FPGAs, reducing parameter complexity to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathcal {O}(2^{k})$</tex-math> </inline-formula> and improving routing efficiency. Our LLNN architectures achieve ultra-low latency—around 2 nanoseconds—on both MNIST and JSC datasets, while maintaining accuracy comparable to state-of-the-art co-designed models. Code available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/capo-urjc/llnn</uri>