A 7-bit Vector-Sum Phase Shifter With Low-Noise Amplifier for LEO Satellite Communication RF Receiver

A 7-bit digital control phase shifter (PS) with a low-noise amplifier using a noise-canceling technique is proposed, operating at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$17\sim 21$ </tex-math></inline-formula> GHz. An interstage matching network is added to reduce the insertion loss, and a loading effect analysis is applied to minimize amplitude/phase unbalance. An analog adder is employed for vector summation with 2-bit sign selection, and biased by two 7-bit current digital-to-analog converters (IDACs), resulting in a 9-bit phase-shift output. By decoding the phase-shift result from 512 states to 128 states, a low-rms phase error of 0.84° can be achieved. The PS is implemented with TSMC 90-nm CMOS technology. It achieves an average gain of 13.5 dB and a noise figure of less than 4.6 dB while consuming 18 mW from a 1.2-V power supply.