Design of a CMOS Power Amplifier With Improved Linearity Through Second-Harmonic Filtering Based on Parasitic Capacitance Analysis

In this study, we investigate linearity enhancement of a differential cascode CMOS power amplifier (PA). First, the variation of parasitic capacitance in the common-source (CS) transistor, which directly affects IMD3 and AM-PM distortion, is analyzed as a function of input power. Then, second-harmonic generation at the gate node of the common-gate (CG) transistors in the differential structure is examined. It is shown that these second-harmonic components alter the parasitic capacitance of the CS transistors, ultimately degrading the linearity of the PA. Based on this observation, a CMOS PA is proposed that improves linearity by incorporating a second-harmonic filter at the gate node of the CG transistors. The proposed PA is fabricated using a 180-nm RFCMOS process. Measurement results at 2.42 GHz with an 802.11n 64-QAM 20 MHz WLAN modulated signal demonstrate an output power of 21.4 dBm and a power-added efficiency (PAE) of 28.6% at an EVM level of 3.98% .