Design and Validation of SystemVerilog I2C VIP with Integrated Assertions and Error Injection Strategies

In this paper, we report the design and verification methodology of a SystemVerilog-based I2C protocol Verification IP (VIP) based not only on assertion-based verification but also on the new checkout error injection techniques. The resulting VIP is designed as a set of loose-coupled modules for protocol description, transaction generation, and automatic protocol checking with SystemVerilog Assertions (SVAs). Timing, multi-master arbitration, and error recovery related to I2C protocol verification challenges are achieved using embedded assertion monitors and focused error injection scenarios on the testbench. The paper describes the inclusion of assertion-based monitors used for checking real-time protocol compliance as well as the ability for systematic error injection to expose corner-case bugs and verify the strength of the DUT and the verification environment. We present our experimental results that demonstrate the effectiveness of proposed strategies on coverage, bug leakage, and reduction in debug cycles. The approach also provides a useful guideline for verification engineers who need to build protocol VIPs or wish to improve the efficiency of their verification flow with assertion-led methods.