Reduction of dynamic on-resistance in GaN-on-sapphire HEMTs using deep trench source and p–n buffer configurations

Abstract GaN-on-sapphire high electron mobility transistors (HEMTs) offer excellent breakdown voltage (BV) due to the insulating substrate, but suffer from dynamic on-resistance ( R ON ) degradation under high drain bias stress ( V DS-Stress ) because the floating substrate promotes electron trapping in the buffer and activates the back-gate effect. We propose a deep trench source combined with a p–n buffer (DTS-pnB) structure to directly address these issues. In this design, the DTS and grounded n-type buffer provide an efficient discharge path for trapped electrons, lowering the negative potential at the buffer bottom, suppressing the back-gate effect, and maintaining a higher potential barrier to inhibit electron injection into carbon-related traps. TCAD simulations show that, under V DS-Stress = 200 V for 100 µ s, the DTS-pnB device exhibits only a 67.7% increase in dynamic R ON , compared with device conduction failure in the conventional structure, while keeping threshold voltage and BV nearly unchanged (∼1000 V). The DTS-pnB design is also compatible with existing GaN-on-sapphire processes and can be implemented with current trench fabrication capabilities, offering a practical route to enhance the dynamic reliability of GaN-on-sapphire HEMTs for high-voltage, high-frequency applications.