Implementation of a PLC Processor Architecture with LLD as Native Language on FPGA and ASIC

Traditional microprocessor-based Programmable Logic Controllers (PLCs) suffer inefficiency when processing Ladder Logic Diagrams (LLD), as they require software translation of this non-native language. This work presents a dedicated Ladder Rung Processor (LRP) architecture that natively executes LLD, eliminating translation overhead. The LRP processes ladder rungs through parallel matrix operations (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times 8$</tex> LSU configuration) with pipelined cyclic scans, achieving deterministic execution. Implemented on both FPGA and 130 nm ASIC platforms without architectural modifications, the design demonstrates cross-platform compatibility. Key results include: (1) FPGA implementation operating at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{5 M H z}$</tex> with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 2. 6} \boldsymbol{\mu}$</tex> s scan time, suitable for industrial control applications; (2) ASIC realization achieving 2 GHz operation with 31.6 ns scans, enabling high-speed automation. The core contributions are: (1) A novel LLD-native processor architecture reducing execution cycles by 27 % versus microprocessor implementations; (2) A unified RTL design validated across FPGA and ASIC technologies; (3) Optimization techniques including memory address swapping and control state reduction that improve throughput by 4 cycles per scan. This hardware-centric approach provides <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$400 \times$</tex> speedup in ASIC versus FPGA implementations while maintaining functional consistency, addressing critical performance limitations in modern PLC systems.