Performance optimization of SiC LDMOS devices with P-top layer

With the rapid advancements in power electronics, the development of high-power semiconductor devices has become a critical field. As a representative of third-generation wide bandgap semiconductors, silicon carbide (SiC) offers significant advantages in high-voltage and high-power applications. In this context, SiC-based lateral double-diffused MOSFETs (LDMOS) are key components in power device systems, and their technological optimization remains a central focus in both academia and industry.In this study, a SiC LDMOS device with a P-top layer was designed and optimized using Silvaco TCAD simulation software. The structures and parameters of both conventional and P-top enhanced LDMOS devices were presented. The effects of P-top layer length, junction depth, and doping concentration on breakdown and output characteristics were investigated. Furthermore, device mechanisms were analyzed from the perspectives of breakdown voltage, surface electric field distribution, and specific on-resistance.The results show that the introduction of the P-top structure significantly improves the breakdown voltage of the SiC LDMOS and leads to a more uniform surface electric field distribution, thereby enhancing device reliability.