A Sub-block Interleaving Algorithm to Mitigate Pilot Interference in LDPC-coded AFDM Systems

High-power pilot symbols are essential for accurate channel state estimation in affine frequency division multiplexing (AFDM) systems, but they introduce significant interference to data symbols. While inserting guard intervals around the pilot symbols can reduce the impact of pilot interference, it comes at the cost of reduced spectral efficiency. This paper proposes a sub-block interleaving algorithm for low-density parity-check (LDPC)-coded AFDM systems that mitigates pilot interference while eliminating guard interval requirements. The algorithm provides differentiated protection at the sub-block level, ensuring sufficient protection for bits that are substantially impacted by pilot interference. The algorithm utilizes feedback from channel estimation and classifies interference-affected bits based on the proposed residual pilot interference model. LDPC sub-blocks are then ranked according to their protection capabilities, which are characterized by unequal error protection (UEP), and matched with the corresponding interference-affected bits. Simulation results demonstrate that the sub-block interleaving algorithm significantly improves bit error rate (BER) performance under various channel estimation conditions.