Synthesis of Mixed-CMOS Very Large-Signal Interconnects with Low Power Consumption

The demand for low-power and high-performance VLSI design has grown significantly with the rise of portable and battery-operated devices.Mixed-CMOS design, which combines the strengths of static CMOS (low power) and Domino logic (high speed and area efficiency), offers a promising solution to address power-performance trade-offs.This paper proposes an influence-based unate decomposition approach for partitioning Boolean logic into unate and binate sub-blocks, which are optimally mapped to Domino and static CMOS styles, respectively.An on-the-fly mapping methodology (CRDOM) with critical path reordering is developed to minimize delay, while a multi-objective particle swarm optimization technique balances delay and area tradeoffs.Furthermore, a pattern recognition-based clock gating technique is integrated to reduce dynamic power consumption with minimal area overhead.Experimental results on benchmark circuits demonstrate significant improvements in terms of power efficiency, area utilization, and performance when compared to conventional static and Domino-only realizations.