A 28nm Digital LDO Based on Improved Successive Approximation Logic Control Algorithm

This paper presents a digital low-dropout regulator (DLDO) architecture employing the improved successive approximation logic algorithm as its control strategy. The algorithm is combined with an asynchronous compensation mechanism to optimize the dynamic response characteristics and reduce the output voltage fluctuation during the transient process. In order to improve the accuracy of the output voltage, a 6-bit Flash ADC is repurposed as the PMOS array unit, enhancing equivalent resolution. The freeze controller is constructed based on the sample-and-hold dynamic comparator to voltage ripple while maintaining consistent robustness against the small load current variations. Measurement results demonstrate the proposed design achieves 0.45-0.85V output regulation under 0.5-0.9V input supply. As the load current is increased from 200uA to 30mA with 1ns edge time, featuring 79mV voltage undershoot, 0.25ns response time with 320ns settling time, and the output voltage accuracy is within 1mV with ripple-free operation.