Design and Evaluation of a Dual Hardware Accelerator System Integrating GPU and FPGA Technologies

There is a growing field around the integration of different embedded components in the context of heterogeneous computing, a paradigm that is defined by having different computing units in the same architecture. The goal was to study how a GPU and a FPGA, both integrated as computing accelerators, would perform around the sample algorithm of image convolution, one that that is heavily used in various data processing and computer vision applications. Different optimizations were applied to the GPU to measure how performance could be impacted and how the optimized results would compare to the overall FPGA performance. The results gave a quantitative 10-15x speedup in relevant speedup and thus allowed an analysis on the strengths of each component. The extension and implementation of this analysis would be an application that would leverage the graphical and computational performance of the GPU system and the flexibility and parallelism of the FPGA. A design requirement and significant hurdle was to establish communication between the two accelerator units in a way that didn't compromise the data or speed. The application was focused on object detection and avoidance through a set of rules and responses.