Low-Noise Low-Power Cascaded Input Comparator for SAR ADC

This paper describes a low-noise, low-power cascaded input comparator suitable for application in SAR ADC design. As the comparator is the main source of noise and power consumption in ADCs, its performance is crucial to the overall efficiency of the system. By analyzing the operation process and noise sources of the traditional two-tailed latch comparator, an improvement scheme is proposed to consider the reduction of noise and power consumption. A multi-stage cascaded input pair is set up in the preamplifier stage to reduce the noise of the preamplifier stage and increase the amplification gain at the same time. In addition, crosscoupling transistors are added to the preamplifier stage to prevent the internal nodes from being completely discharged, thereby reducing the power consumption. The proposed comparator is designed in TSMC 65nm process with a layout area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$7.52 \mu ~\mathrm{m} \times 15.16 \mu ~\mathrm{m}$</tex>. Simulation results show that the comparator has an input equivalent noise of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$233 \mu ~\mathrm{V}$</tex> and an average power consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$17.52 \mu ~\mathrm{W}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{VDD}=1.2 ~\mathrm{V}, \quad \text{VCM}=0.6 ~\mathrm{V}$</tex>, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{fs}=500 \text{MHz}$</tex>.