A high-speed, high common-mode noise immunity level shift circuit

To ensure signal integrity during the conversion process, a high-speed level-shifting circuit with high common-mode noise immunity was designed for the half-bridge gate drive circuit in a GAN system. The circuit employs a cross-coupled structure to suppress the transmission of common-mode noise currents, significantly improving the common-mode noise immunity of the high-voltage gate driver (HVIC). Additionally, a differential-mode noise suppression structure is adopted to effectively reduce the impact of circuit mismatches on signal transmission. Furthermore, V-I-V technology is utilized to enhance the circuit’s performance against negative VS voltage. The design is based on a $0.35 \mu \mathrm{~m}$ BCD process. Simulation results demonstrate that the designed HVIC achieves a dv/dt noise immunity of $200 \mathrm{~V} / \mathrm{ns}$ and allows a VS negative bias voltage of -7.5V under a 15V power supply. Compared to traditional level-shifting circuits, the proposed design optimizes transmission delay. Under a 600V high-voltage condition, the rising-edge transmission delay is 13ns, and the falling-edge transmission delay is 9ns.