Research on K-band High-Linearity Power Amplifier Chip Based on InP DHBT

This paper presents the design of a highly linear power amplifier operating from $17.7-21.2 \mathrm{GHz}$, fabricated using a $0.7 \mu \mathrm{~m}$ InP DHBT process. A hybrid-biased Cascode topology is employed to enhance breakdown voltage capability, enabling the collector bias voltage to be increased from 2 V to 4 V. To address base operating point drift in the Cascode stage, an improved adaptive biasing network based on a current mirror is proposed. This network effectively stabilizes the DC operating point and improves linearity. Efficient impedance matching is achieved in the design through the implementation of RC equivalent models. The fabricated circuit occupies a compact chip area of $1.5 \mathrm{~mm} \times$ 1.9 mm. Simulation results demonstrate a maximum saturated output power of 21 dBm and a peak power-added efficiency of 43.4% within the operating band. Under a 3 dB output power back-off condition, the third-order intermodulation distortion remains below -35 dBc across the entire frequency band. This work provides an effective solution for achieving high linearity in millimeter-wave power amplifiers.