Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

Gated Hall measurements are conducted to calculate interface trap density of a nitric oxide (NO) annealed 4H silicon carbide (4H-SiC) MOSFET. The free carriers are measured using split CV method. Application of body bias confirms that the total trap quantity does not change at the interface when changing the electric field through body bias for a given device. The effect of positive gate stress on Hall mobility is also studied. A stress voltage of +36 V is applied for different stress times (0, 10, 30, 100, and 300 sec). With the increased stress time, the Hall mobility value drops at low gate voltages, while at higher gate voltages they merge. Higher stress creates more interface traps that in turn increase Coulomb scattering which lowers mobility at low gate voltages. The effect of gate stress on Hall mobility provides accurate insight of the channel behavior due to interface traps at 4H-SiC / SiO 2 interface.