Design and Implementation of SRAM on FPGA and Verification Using UVM

This research focuses on the design, verification, and implementation of a 6T SRAM using HDL, UVM, and FPGA for performance optimization. A reusable UVM testbench ensures thorough verification of read and write operations, while coverage-driven verification verify all possible scenarios. System Verilog assertions enhance design correctness. The 6T SRAM model is simulated and synthesized using Vivado for functional verification. Additionally, a comparative analysis of 6T SRAM, Dual port 6T SRAM (DSRAM), and Pseudo static RAM (P6T SRAM) is conducted, focusing on power consumption, speed, and area utilization. The aims to develop an efficient memory architecture for high-speed, low-power applications, ensuring reliability and improved performance in digital systems.