Design of an L-Band Low-Power Low-Noise Amplifier Chip

This paper presents a low-power, low-noise amplifier (LNA) chip fabricated in a $0.25 \mu \mathrm{~m}$ GaAs pHEMT process. The proposed design employs a current-reuse architecture to significantly reduce the drain current, thereby achieving low power consumption. An active bias circuit is integrated to stabilize the DC operating point and suppress performance variations caused by environmental factors. Additionally, a hybrid topology combining parallel negative feedback with inductive peaking is proposed, where peaking inductors are embedded into the feedback path to form a composite network. This approach simultaneously optimizes gain flatness and broadband characteristics. Post-layout simulations demonstrate that the LNA operates in the L-band with a power consumption of 23.8 mW, a gain of 30 dB, and a noise figure as low as 0.6 dB, while maintaining unconditional stability across the entire bandwidth. Compared to existing designs, this work exhibits superior performance in terms of gain, noise figure, and power efficiency, making it suitable for high-performance RF front-end systems.