STAP Acceleration Method Based on Explainable Network Design and Hardware Deployment Verification

In order to solve the problem of the surge in computational complexity of the space-time adaptive processing (STAP) algorithm in space-based radar ground detection under complex clutter background, this paper proposes a STAP acceleration method based on interpretable network design. This paper decouples the iterative maximum likelihood estimation process of the covariance matrix into an interpretable neural network layer, integrates prior information such as platform speed and yaw angle to construct a dynamic modulation network. Based on the training and verification of measured space-based radar data, the covariance matrix estimation time is reduced to 0.21 ms in the $128 \times 128$ space-time dimension, and the clutter suppression performance is improved to $\mathbf{1 2. 6 d B}$. The method was deployed on Huawei Ascend 910B NPU platform and verified on 310B. Through computational graph optimization, the DSP utilization was controlled at $\mathbf{6 2 \%}$ and the BRAM occupancy rate was 23%, achieving the optimal balance point of memory reuse.

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Publication Details

Published
2025-06-27
DOI
https://doi.org/10.1109/icetis66286.2025.11144019
Primary Topic
Big Data and Digital Economy
Type
article
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article

STAP Acceleration Method Based on Explainable Network Design and Hardware Deployment Verification

Wenjia Liu, Qin Yi
Big Data and Digital Economy
article

STAP Acceleration Method Based on Explainable Network Design and Hardware Deployment Verification

Wenjia Liu, Qin Yi
article en

Abstract

In order to solve the problem of the surge in computational complexity of the space-time adaptive processing (STAP) algorithm in space-based radar ground detection under complex clutter background, this paper proposes a STAP acceleration method based on interpretable network design. This paper decouples the iterative maximum likelihood estimation process of the covariance matrix into an interpretable neural network layer, integrates prior information such as platform speed and yaw angle to construct a dynamic modulation network. Based on the training and verification of measured space-based radar data, the covariance matrix estimation time is reduced to 0.21 ms in the $128 \times 128$ space-time dimension, and the clutter suppression performance is improved to $\mathbf{1 2. 6 d B}$. The method was deployed on Huawei Ascend 910B NPU platform and verified on 310B. Through computational graph optimization, the DSP utilization was controlled at $\mathbf{6 2 \%}$ and the BRAM occupancy rate was 23%, achieving the optimal balance point of memory reuse.

Shanghai Industrial Technology Institute (CN)
Openalex Percentile: Top 65%
Big Data and Digital Economy
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