In-Situ Surface Energy Engineering for ALD-Derived Highly Reliable Top Gate In ₂ O ₃ Thin-Film Transistors

This study investigates the effects of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-situ</i> surface energy engineering applied prior to the deposition of the top gate dielectric on the electrical performance of In<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> TFTs. O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma treatment effectively reduces the interfacial trap density at the In<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>/gate dielectric interface, enhancing the overall device performance. Notably, In<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> TFTs subjected to an optimized oxygen plasma treatment duration of 3 sec exhibited significant improvements in electrical characteristics, including a high field-effect mobility of 84.3 cm²/V·s, a steep subthreshold swing of 76.8 mV/dec, and a minimal threshold voltage shift of 20 mV under rigorous bias temperature stress conditions (an electric field of 4 MV/cm at 85 °C for 3600 sec).