Performance Optimization of Short-Channel Top-Gate Ultrathin InSnO Thin-Film Transistor With Gate Dielectric Engineering

High-performance top-gate ultrathin InSnO (ITO) thin-film transistors (TFTs) are investigated using gate dielectric engineering. The optimized device exhibits a high carrier mobility of about 51.7 cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>/V·s. Furthermore, the scaled device with a channel length of 90 nm is demonstrated, showing a high on/off current ratio of ~10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup>, a decent threshold voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub>) of -0.31 V, and a remarkable on-state current of 1389 μA/μm. An excellent positive bias stress stability has also been achieved, presenting a small <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift of -192 mV after 60 minutes of stress at 2 MV/cm. Finally, the device exhibits minimal variation after 6 months of atmospheric storage. These results suggest that the top-gate ITO TFTs have significant potential for monolithic 3-D integrated circuits.