A 4–400 K CMOS Voltage and Current Reference With Single-Transistor Noise-Suppression Loop

This paper presents a chopping-less CMOS-based voltage and current reference with a single-transistor noise-suppression loop, where the overall noise is determined by a single transistor while the other noise sources are all suppressed by the gain of the transistor. The reference voltage and current exhibit integrated noises of 2.16μV and 20.3pA with noise floors of 0.45μV and 4.2pA. The chip shows temperature coefficients (TC) of 239.4ppm/°C for the reference voltage (V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REF</sub>) and 362.8ppm/°C for the reference current (I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REF</sub>) over a temperature range of -40°C to 140°C. The chip was also verified for cryogenic applications for use in quantum computing systems, over a range of 4K to 200K, showing TCs of 317.9ppm/K for V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REF</sub> and 315.7ppm/K for I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REF</sub>.