An Optimized Hardware Implementation of ASCON With Power Analysis Attack Resistance

ABSTRACT In recent times, the security of data collected and transmitted by IoT nodes has gained high importance. Hence, a lightweight cryptographic algorithm is required to be implemented in such nodes. ASCON is one such lightweight cryptographic algorithm selected by NIST and a winner of CAESAR. The ASCON‐128 and ASCON‐128a are implemented in two different styles on both FPGA and ASIC platforms with a minimum area. A power analysis attack is mounted on the FPGA implementation of ASCON‐128, and the 128‐bit key is successfully extracted with 460 power traces. To mitigate the power analysis attack, the Hamming weight and thus the Hamming distance of the data are made uniform using the 1‐of‐4 encoding technique, incorporated in the hardware implementation as a countermeasure against those attacks. The proposed and secured hardware implementation of ASCON‐128 consumes a minimum area of 41.195‐kilogate equivalent and 13.5‐mW power compared to works in the literature, making it preferable for IoT applications.