Development of a Novel Warpage Control Method for Epi-Ready 4H-SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces

We have demonstrated a novel process that precisely controls the wafer bow, a key parameter of overall warpage, of 4H-SiC wafers to any desired value by integrating a thermal sublimation process, Dynamic AGE-ing® (DA), immediately prior to the CVD epitaxial process. This method achieves atomic-level flatness of the CMP-finished surface independent of the growth and etching amounts, while concurrently eliminating sub-surface damage (SSD). When DA is applied to simultaneously etch the Si-face and grow the C-face, the wafer bow decreases linearly with increasing C-face growth. In wafers with poorer mechanical processing quality, an increase in bow is observed for C-face growth below 120 nm, likely due to the relaxation of SSD on that side. The process also removes SSD from the Si-face, ensuring that both sides are sufficiently cleared of damage. Furthermore, for wafers with an initially negative bow, simultaneous Si-face growth and C-face etching using DA produces a linear increase in bow. By applying these processes, we successfully adjusted the bow to –0.4 µm on an 8-inch wafer that initially measured –12.0 µm. These results indicate that, regardless of the initial bow severity, precise control of the wafer bow can be achieved without adversely affecting subsequent CVD epitaxy processes by appropriately managing the growth layer thicknesses on both faces using DA.

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Publication Details

Journal
Materials science forum
Published
2025-09-04
DOI
https://doi.org/10.4028/p-js5aam
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
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article

Development of a Novel Warpage Control Method for Epi-Ready 4H-SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces

Daichi Dojima, Kohei Toda, Tadaaki Kaneko, S. C. Jeong
5 links
Materials science forum
Silicon Carbide Semiconductor Technologies
article

Development of a Novel Warpage Control Method for Epi-Ready 4H-SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces

Daichi Dojima, Kohei Toda, Tadaaki Kaneko, S. C. Jeong
article en

Abstract

We have demonstrated a novel process that precisely controls the wafer bow, a key parameter of overall warpage, of 4H-SiC wafers to any desired value by integrating a thermal sublimation process, Dynamic AGE-ing® (DA), immediately prior to the CVD epitaxial process. This method achieves atomic-level flatness of the CMP-finished surface independent of the growth and etching amounts, while concurrently eliminating sub-surface damage (SSD). When DA is applied to simultaneously etch the Si-face and grow the C-face, the wafer bow decreases linearly with increasing C-face growth. In wafers with poorer mechanical processing quality, an increase in bow is observed for C-face growth below 120 nm, likely due to the relaxation of SSD on that side. The process also removes SSD from the Si-face, ensuring that both sides are sufficiently cleared of damage. Furthermore, for wafers with an initially negative bow, simultaneous Si-face growth and C-face etching using DA produces a linear increase in bow. By applying these processes, we successfully adjusted the bow to –0.4 µm on an 8-inch wafer that initially measured –12.0 µm. These results indicate that, regardless of the initial bow severity, precise control of the wafer bow can be achieved without adversely affecting subsequent CVD epitaxy processes by appropriately managing the growth layer thicknesses on both faces using DA.

Materials science forumVol. 1156
Kwansei Gakuin University (JP)
Openalex Percentile: Top 77%
Silicon Carbide Semiconductor Technologies
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Development of a Novel Warpage Control Method for Epi-Ready 4H-SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces — Daichi Dojima, Kohei Toda, et al. · Materials science forum (2025) | TGRS Research Map | TGRS