A Novel Serial Peripheral Interface Master Core

This research presents the design of Serial Peripheral Interface master core. It is a commonly used communication protocol that allows serial data transfer between a master and multi-slave device over a short distance. In this paper, we will focus on block-level architecture and develop RTL code for the same. This controller is developed using Verilog HDL based on the IEEE standards and also verified using Verilog HDL code. The main part of the SPI master core is to generate the serial clock which will be derived from the wishbone master clock. SPI protocol works with Master-Slave configuration, in full duplex mode. This is a 4-wire transmission that includes "SCLK, MOSI, MISO, SS". MOSI will transfer the bit serially from the SPI master core to the SPI slave and MISO will receive the serial bit from the SPI slave to the SPI master.