GAAFET-based Hybrid Sense Amplifier for High Speed Applications

This paper introduces an innovative Hybrid sense amplifier design, integral to optimizing the SRAM read operation. For a current mode sense amplifier, the delay caused for read operation in SRAM is more compared to Voltage mode sense amplifier. On the other hand, Voltage mode sense amplifier has a drawback of higher operational failure. Hence a hybrid of multimode sense amplifier can improvise the overall performance. This comparative analysis of Sense Amplifier design using different FET devices and technology nodes will inform the selection of the most suitable technology to achieve the desired power efficiency and operational speed improvement. Thus, the introduced High Speed Hybrid Multimode Sense Amplifier for SRAM Applications will also be able to perform better than the existing design in terms of the overall power-delay product. All the designs will be simulated using Synopsys HSPICE tool at lower technology nodes. Performance analyses will be done with respect to power, delay, and power-delay product.