Error-Tolerant Arithmetic Circuit Design for Energy Efficient Computing

Approximate adders have earned prominence in the modern Very Large-Scale Integration(VLSI) design due to their ability to reduce the usage of power, and their ability to improve the computational speed, and in minimizing the circuit complexity. However, in image processing applications, output accuracy is not a major concern and can be subject to considerable variation. This study in depth explains the evaluation and design of the proposed Approximate Full Adder(AFA),which optimizes the efficiency of circuit by reducing power, area, and the computational delay while maintaining acceptable computational accuracy. The gate-level circuit simulations were done using Cadence Encounter® RTL Compiler v12.10− s012<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</inf> with 45 nm technology, and power, delay, and area, were evaluated. Here when it comes to performance metric of image procesing application such as Peak Signal-to-Noise Ratio(PSNR),Mean Squared Error(MSE),and the Structural Similarity Index(SSIM) demonstrate the adder’s effectiveness in the image processing applications with help of python code in google colab platform. The result displays that the proposed design reduces the area of the cell by 58.33% and the consumption by 58.80% when it is compared to the previous designs, then making it more suitable for low-power VLSI applications.