Design and Implementation of Optimized Inexact Signed Wallace Tree Multiplier Using Reversible Logic Gates and 4:2 Compressors

The Wallace tree multiplier is a crucial component of digital signal processing and arithmetic circuits due to its high-speed multiplication capabilities. In order to increase performance parameters like error distance, power consumption, delay, and area, the suggested architecture offers an upgraded Wallace tree multiplier that incorporates compressors and reversible logic gates. Conventional logic gates are used in traditional Wallace tree multipliers, which results in considerable heat generation and power consumption. Since reversible logic gates should ideally use no power, the suggested design minimizes power loss by incorporating them, which guarantee bijective mapping between input and output vectors. The multiplier's total speed and efficiency are further optimized by the use of compressors during the partial product reduction phase. Design is also analysed for efficiency using metrics like Quantum Cost (QC), Constant Inputs (CI), Garbage Outputs (GO) and Gate Count (GC). To further improve efficiency, the work proposes new architectures for a key component called the Reversible Inexact 4:2 compressor. This design is designed specifically for reversible logic and offers only +1 or -1 of error distance with decreasing Quantum cost of 21.8%, decreasing Garbage outputs of 34.8%, decreased power of 0.312 Watts (36.3%) and decreased delay of 0.276ns (4.5%) when compared to existing Inexact 4:2 compressor. By optimizing the design, we achieve improved performance of Wallace tree multiplier by reduced power of 0.868Watts (7%) and decreased delay of 0.509ns (5.6%). we achieve improved performance of Wallace tree multiplier by decreasing 11 LUTS in Area utilization while comparing with existing Wallace tree multiplier. The Vivado tool with Artix-7 board is used to determine these parameters.