Performance optimization of power MOSFETs in SMT top-side-cooling packages by system design

This work presents easily applicable practices for optimizing the performance of power converters using discrete, top-side-cooled power packages. It demonstrates how parasitic elements in the power path can be minimized, using a full-bridge topology with novel Silicon-Carbide wide bandgap power semiconductors as an example. Furthermore, this paper explores two different methods for estimating power-loop inductances: one measurement based, and one simulation-based method. With the mismatch between the results being less than 10 percent, a total power-loop inductance of 7 nH (on average) could be achieved with the Silicon-Carbide second generation (G2) Power MOSFETs in Q-DPAK packages. Finally, suggestions for further optimization of the test board are offered. The recommendations and best practices outlined in this paper provide valuable insights for designers and developers of power conversion systems, facilitating faster design-in cycles for top-side-cooled power packages across various applications.