Design of Adders Using Pass Transistor Logic for Wallace Tree Multiplier in 45nm Process

This work presents the design and analysis of low-power, high-performance adders, and a Wallace Tree Multiplier implemented in 90 nm and 45 nm CMOS technologies. Key components, including AND gates, half adders, and full adders, were optimized using novel techniques to reduce transistor count, delay, and power consumption significantly. The transistor count for the entire design was minimized to 240 transistors. Delay improvements were notable, with half adders showing 18.85 ps at 90 nm and 13.58 ps at 45nm, and full adders achieving 23.59 ps at 90 and 3.524 ps at 45 nm. Power consumption was significantly reduced, with half adders consuming 382.4 nW at 90 nm and 47.10 nW at 45 and full adders consuming 667 nW at 90nm and 148.6 nW at 45 nm. The Wallace Tree Multiplier demonstrated a delay of 18.03 ns in 90 nm and 31.72 ps in 45 nm, with power dissipation reduced to 300 pW and 4.51 pW, respectively. These results showcase how well the proposed designs meet minimal power consumption and high efficiency, making them suitable for advanced digital applications