FSM Based Implementation of March C- and Checkerboard Algorithm

Embedded memory systems are integral to modern VLSI designs, constituting a significant portion of chip area and directly impacting system reliability and performance. As semiconductor memories become denser and operate at higher frequencies, they are increasingly prone to various faults such as stuck-at, transition, coupling faults etc. Undetected memory failures can lead to critical system malfunctions, making efficient memory testing a fundamental requirement in hardware verification and validation. To ensure robustness, various memory testing algorithms have been developed, often serving as the foundation for Memory Built-in Self-Test (MBIST) methodologies. In this paper, we analyse the FSM (finite state machine) based FPGA implementation of two widely used memory test algorithms, March C- and Checkerboard, and assessing their efficiency in terms of area, power consumption, and delay. These algorithms are implemented in Verilog, synthesized on Xilinx Vivado – 2016.2, and deployed on the Nexys 4 DDR Artix-7 FPGA. Our results provide a comparative evaluation of these algorithms, demonstrating their effectiveness in detecting memory faults and highlighting their suitability for FPGA-based memory testing and verification.