Design and Implementation of a Hazard-Resilient ARM Processor with Pipeline for FPGA

An Advanced RISC Machine (ARM) processor is based on a Reduced Instruction Set Computing (RISC) architecture, which is recognized for its power efficiency and high performance. It is commonly found in mobile devices, embedded systems, and IoT applications. Pipelining breaks down instruction execution into several stages: fetch, decode, execute, memory access, and write-back. This method enables concurrent execution, enhancing throughput and speed. However, pipeline hazards, such as data, control, and structural hazards, can effect performance. Data hazards occur when instructions are relayed on the results of previous ones. Control hazards arise from branch instructions, while structural hazards arise from competition for resources. This project simulates and synthesizes an ARM processor pipeline using Verilog and Xilinx Vivado. Techniques for mitigating hazards are applied, including forwarding, stalling, and branch prediction. The results demonstrate improved throughput and decreased execution time, leading to optimized pipelined designs.