Design of Low Dropout Regulator using SCL 180nm Technology for Power Management Integrated Circuit

The paper explores the design of an Analog Low Dropout Regulator using SCL 180nm CMOS technology. It is a type of linear regulator that can operate when the input and output voltage difference is small. This basic topology consists of a reference voltage, error amplifier, pass transistor, resistor divider network and a miller compensation network. The objective of the work is to design a 1.2V regulated voltage from a 1.8 V source with enhanced stability. The LDO reduces high frequency supply noise without requiring a large external capacitor. The miller capacitor will act as the dominant pole in this C-free structure. The noise contributions of error amplifier is reduced by widening the input MOSFETs. The LDO possess a line regulation of 4mV/V, load regulation of 6.316 mV/A and good stability with 1-20 mA load.