Design and Simulation of a High-Speed, Power-Efficient 8-bit Flash Analog-to-Digital Converter

ADC plays a vital role in signal processing applications where the analog signal is converted to a digital signal that can be encrypted for use in fields like military and telecommunications. This paper presents the design and simulation of a low-power, high-speed 8-bit Flash Analog-to-Digital Converter (ADC) optimized for a sampling frequency of 25 MHz The Coarse Fine technique with folding circuit is used to reduce the number of resistors and comparators compared to traditional Flash ADCs. Moreover, the coarse fine design decreases the power consumption without compromising performance. Cadence Virtuoso with GPDK 180 technology libraries are used in simulation. Simulation shows that 15 mW of power consumption, 3.16 nS of delay, and overall processing performance critical for applications in military and telecommunications.