FPGA Based Performance Evaluation of Primitive Block Ciphers of the NIST LWC Standardization Finalists

Lightweight cryptographic algorithms are essential for securing resource-constrained IoT devices, where hardware efficiency is crucial to balancing security, power consumption, and computational performance. This paper presents a comparative FPGA-based analysis of primitive block ciphers from the NIST Lightweight Cryptography Standardization Finalists, focusing on key performance metrics such as resource utilization (LUTs, FFs, SLCs), maximum operating frequency, throughput, and power consumption (static and dynamic). The results highlight trade-offs between high-speed performance and energy efficiency, with certain ciphers excelling in throughput while others offer lower power consumption and resource overhead. This study provides valuable insights into selecting optimal cryptographic solutions for IoT and embedded systems. Future research will explore side-channel resistance techniques and hardware optimizations to enhance the security and efficiency of FPGA-based cryptographic implementations.