A Direct-to-Digital Readout Architecture for CMOS Hall Sensors

This paper presents a monolithic integrated direct-to-digital readout architecture for Hall sensors. The ADC is connected directly to the current spinning Hall cell by means of Gm-C techniques to avoid interfering with the sensor. By making use of the inherent anti-aliasing function of the feedback compensated continuous-time sigma-delta (CT ΣΔ) converter, notch filters can be effectively realized in the digital domain to suppress offset without introducing aliasing effects. The flash-based inner quantizer allows the upmodulated signal to be converted and thus enables digital-only demodulation, limiting the residual offset to that of the sensor and removing the necessity of digital offset ripple loops. By using a sinusoidal signal for demodulation, an offset of 11 μT (1σ) is obtained without compromising on noise level within a ±60 mT range and a 65 kHz bandwidth. The architecture achieves a FOM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DR</sub> of 130 dB, comparable to the best recent state-of-the-art CMOS Hall sensors, while featuring a low supply voltage of 1.5 V, the smallest area and at least 2.6x improvement in power consumption.