Design and Simulation of Area Optimized Sense Amplifier for Memory Array

Memory arrays are vital components in modern digital systems, demanding high-speed and low-power operation for efficient data storage and retrieval. Sense amplifiers play a critical role in achieving these objectives by minimizing sensing delay and ensuring reliable performance under varying conditions. This paper proposes two PMOS-biased current-based sense amplifiers, emphasizing compact design and reliable performance under temperature variations. Simulations were conducted in Cadence Virtuoso with the gpdk 180nm library, analyzing transient behavior and sensing delay. The results demonstrate distinct trade-offs between the two designs, providing key considerations for optimizing sense amplifiers in memory systems.