A Novel Reversible 16X8 SRAM Array using Gate Diffusion Input Logic

Reversible logic circuits enable a bijective mapping between inputs and outputs, ensuring lossless computation and facilitating the retrieval of input states from output states. This property significantly reduces bit loss, leading to reduced power required for low-power and high-speed computing applications. The proposed reversible logic based 16X8 SRAM array design using gate diffusion input (GDI) is implemented with V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf>=1.2V using mentor graphics at 130nm technology. It shows 59.63% efficiency in PDP compared to CMOS logic, 27.389% increased compared to transmission gate logic (TGL) and 50.58% improvement compared to pass transistor logic (PTL) based SRAM array. SRAM array designed using reversible gates are analyzed using TGL, GDI, PTL and compared with conventional CMOS logic.