Performance Evaluation of MFIS and MFMIS Negative Capacitance FDSOI for Low Power Applications

Fully Depleted Silicon On Insulator (FD-SOI) technology offers significant advantage over conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in terms of low leakage current, high speed and low power dissipation. The planar technology used to fabricate these devices makes them an attractive option over Fin Field Effect Transistors (FinFETs) for low power low cost devices. Combining the FDSOI with negative capacitance effect results in enhancing the speed and reducing the power dissipation further. This paper presents the comparative study of two different structures of negative capacitance FDSOI (NC-FDSOI) in 20nm technology namely Metal Ferroelectric Metal Insulator Semiconductor (MFMIS) and Metal Ferroelectric Insulator Semiconductor (MFIS) structures using Sentaurus TCAD. Increased on current and reduced subthreshold swing is observed for MFMIS structures as compared to MFIS structures at increased ferroelectric thickness. Complementary Metal Oxide Semiconductor (CMOS) circuits are simulated with these devices to observe the timing behavior and it is found that MFMIS structure offers superior timing response compared to MFIS structure.