Parallel Connection of Low-Voltage GaN FET for High-Current Power Converters

This paper investigates the switching transients in parallel connection of low voltage GaN FETs to perform a high-current switch. The current unbalance is evaluated by the use of two suitable experimental boards with several GaN FETs connected in parallel in two different ways. In the first solution the GaN FETs are paralleled to obtain a single switch connected in a switching pole with inductive load. A testing methodology has been developed to evaluate the contribution of the parasitic capacitances in the transient current behaviour. In the second solution four switching legs composed by high side and low side GaN FET devices are arranged to reduce the inductive stray inductances. The second board prototype is designed to investigate the effects of switching gate delay time at various load current levels. In the two boards, every device can be driven independently, and a source shunt per each GaN FET monitors the transistor current. Simulation results and experimental tests are carried out to comprehensively evaluate the devices' imbalance due to different delay times of the gate control signals. The turn-on and turn-off switching transients are considered. The parasitic capacitances effect, the stray inductances and the load current level influence in the switching transients are explored, providing guidelines for optimizing the performance of GaN FET devices in parallel connections.