StatCHAR: Statistical Timing Characterization Framework via Heterogeneous Graph Attention Network and Active Learning With Parasitic RC Reduction

Statistical timing characterization for standard cell library poses significant challenges to accuracy and runtime cost. Prior analytical and learning-based methods neglect the profound influence induced by the layout-dependent parasitic resistor and capacitor (RC) network in cell netlist as well as the timing correlation between the topological structures of cells and process, voltage, and temperature (PVT) corners for model training, resulting in tremendous simulation effort and poor accuracy. In this work, a Statistical timing Characterization framework via Heterogeneous graph attention network and Active learning with parasitic RC Reduction (StatCHAR) is proposed, where the transistors and parasitic RC in cell are represented as heterogeneous nodes for graph learning and redundant RC nodes are removed to alleviate node imbalance issue and improve accuracy. The significant training data are selected from the full characterization set with active learning strategy to achieve the optimal balance between simulation overhead for the training set and prediction precision for the remaining test set. The proposed framework was validated with typical standard cells under multiple PVT corners with TSMC 22nm process, which achieves an excellent prediction with a relative Root Mean Square Error (rRMSE) of only 2.43% with only 11.9% of total characterization data for training, demonstrating an accuracy improvement of 2.7<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times \sim 12.1\times $</tex-math> </inline-formula> for statical timing analysis on benchmark circuits compared to competitive learning based methods and a characterization runtime reduction by 7.5<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $</tex-math> </inline-formula>.

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Publication Details

Journal
IEEE Transactions on Circuits and Systems I Regular Papers
Published
2025-09-04
DOI
https://doi.org/10.1109/tcsi.2025.3604138
Citations
1
Primary Topic
Algorithms and Data Compression
Type
article
Field-Weighted Citation Impact
2.48

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article

StatCHAR: Statistical Timing Characterization Framework via Heterogeneous Graph Attention Network and Active Learning With Parasitic RC Reduction

Xu Cheng, Jun Yang, Peng Cao, Yuyang Ye et al.
1 citations
IEEE Transactions on Circuits and Systems I Regular Papers
Algorithms and Data Compression
2.48
article

StatCHAR: Statistical Timing Characterization Framework via Heterogeneous Graph Attention Network and Active Learning With Parasitic RC Reduction

Xu Cheng, Jun Yang, Peng Cao, Yuyang Ye, Yuhan Dong, Zeyuan Deng
article en
1 citations

Abstract

Statistical timing characterization for standard cell library poses significant challenges to accuracy and runtime cost. Prior analytical and learning-based methods neglect the profound influence induced by the layout-dependent parasitic resistor and capacitor (RC) network in cell netlist as well as the timing correlation between the topological structures of cells and process, voltage, and temperature (PVT) corners for model training, resulting in tremendous simulation effort and poor accuracy. In this work, a Statistical timing Characterization framework via Heterogeneous graph attention network and Active learning with parasitic RC Reduction (StatCHAR) is proposed, where the transistors and parasitic RC in cell are represented as heterogeneous nodes for graph learning and redundant RC nodes are removed to alleviate node imbalance issue and improve accuracy. The significant training data are selected from the full characterization set with active learning strategy to achieve the optimal balance between simulation overhead for the training set and prediction precision for the remaining test set. The proposed framework was validated with typical standard cells under multiple PVT corners with TSMC 22nm process, which achieves an excellent prediction with a relative Root Mean Square Error (rRMSE) of only 2.43% with only 11.9% of total characterization data for training, demonstrating an accuracy improvement of 2.7<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times \sim 12.1\times $</tex-math> </inline-formula> for statical timing analysis on benchmark circuits compared to competitive learning based methods and a characterization runtime reduction by 7.5<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $</tex-math> </inline-formula>.

IEEE Transactions on Circuits and Systems I Regular PapersVol. 73(3)
Chinese University of Hong Kong (HK), Southeast University (CN)
National Natural Science Foundation of China
Openalex Percentile: Top 9%
Algorithms and Data Compression
2.48
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