Initial Insights into Synthesis Overheads Caused by C-Based Error Correction Codes Implementations

Error Correction Codes (ECCs) are increasingly used in safety-critical systems, such as hardware accelerators for cryptographic computations and neural network inference. These systems require high reliability, making ECCs essential for mitigating soft errors and improving fault tolerance. Thus, the demand for efficient ECC implementations is rising, necessitating faster design and deployment processes. Traditional hardware design approaches, such as Register-Transfer Level (RTL) development, can be time-consuming and very complex. High-Level Synthesis (HLS) enables the automatic transformation of C-based ECC models into hardware descriptions, reducing development effort while allowing design-space exploration. This methodology facilitates rapid prototyping and optimization, enabling the evaluation of different architectural choices without manually modifying the RTL code. However, coding styles, algorithmic transformations, and optimization strategies in C-based can directly affect the synthesized hardware's performance metrics, including area utilization, power consumption, and latency. This work provides initial insights into how different C-based ECC design choices influence the final hardware implementation. To do this, we have analyzed synthesis results under various ECC configurations.