Towards SW-Based Robustness Assessment of HW Accelerators for Quantized CNNs

Quantized Convolutional Neural Networks (QCNNs) are widely adopted in resource-limited environments due to their reduced memory footprint, lower power consumption, and faster execution. Hardware (HW) accelerators further enhance these benefits by optimizing QCNN execution for available resources, a crucial aspect in embedded systems. Typically, the development of neural networks begins with a software (SW) model, later refined and implemented in HW. Leveraging this initial SW model for early robustness assessments is an attractive approach, as it allows fault tolerance evaluation before committing to HW implementation. However, for such assessments to be meaningful, they must accurately reflect the fault behavior in HW. This paper examines the limitations of naive fault injection in SW-based QCNN models and demonstrates how they can lead to misleading conclusions about HW robustness. The key issue arises from the internal multi-component representation of quantized parameters, which differs from direct floating-point storage. Our analysis highlights that simplistic bit-flip injections in SW do not necessarily translate to equivalent faults in HW, leading to inaccuracies in robustness evaluation. While we do not propose a specific fault injection methodology, we identify critical challenges that must be addressed to ensure that early-stage SW evaluations provide valid, cost-effective insights into QCNN resilience in HW.