Ultrascaled Monolayer α -CS and SiP 2-D n-Type FETs: Performance Enhancement via Underlayer Modulation Beyond 5-nm Technology Nodes

The relentless miniaturization of field-effect transistors (FETs) necessitates the development of novel materials and architectures to address the challenges posed by short-channel effects (SCEs) and power inefficiencies. This investigation examines the performance of sub-5-nm monolayer α-CS and SiP double-gated (DG) n-type FETs utilizing underlayer (UL) modulation, an approach that has not been previously explored for these materials at such scales. Through the application of density functional theory (DFT) and nonequilibrium Green’s function (NEGF) simulations, we illustrate that the integration of UL significantly enhances the subthreshold swing (SS), ON–OFF ratio (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub>/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>off</roman></sub>), delay (τ), and power delay product (PDP). The integration of UL helps achieve the International Technology Roadmap for Semiconductor (ITRS) HP device requirements and improves the overall performance of the sub-5-nm monolayer α-CS and SiP DG n-type FETs. For devices with a gate length of 3-nm and 2-nm UL modulation achieves an (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub>/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>off</roman></sub>) of <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</roman>.<roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">34</roman>×<roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</roman><sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>4</i></sup> for α-CS and <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</roman>.<roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">57</roman>×<roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</roman><sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>4</i></sup> for SiP, with SS values as low as 108 mV/dec for α-CS and 101 mV/dec for SiP. These findings exceed the ITRS 2028 Horizon targets, positioning α-CS and SiP as premier candidates for high-performance (HP) logic applications. The study offers essential insights into UL-driven electrostatic control, thereby addressing a critical challenge in the design of ultrascaled 2-D n-type FETs.