A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces

This work presents a command-aware hybrid low-dropout regulator (CA-HLDO) designed to mitigate voltage droop and power-supply-induced jitter (PSIJ) in write DQS (WDQS) buffers for high-bandwidth memory (HBM) interfaces. In HBM standards, WDQS buffers experience abrupt load current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {L}}$</tex-math> </inline-formula>) transitions, leading to significant voltage droop in the environment of the complexity of the power delivery network (PDN). However, conventional analog LDOs (ALDOs) and event-driven LDOs (ED-LDOs) suffer from a limited loop bandwidth, making it difficult to prevent large voltage droops and PSIJ degradation. To address these challenges, the proposed CA-HLDO leverages a unique property of memory systems: the magnitude and timing of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {L}}$</tex-math> </inline-formula> are deterministic based on commands from the host. Exploiting this property, the CA-HLDO proactively sources a current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {D}}$</tex-math> </inline-formula>) that matches <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {L}}$</tex-math> </inline-formula> precisely at the time of its occurrence, thereby minimizing voltage droop and reducing the settling time (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm {S}}$</tex-math> </inline-formula>). The architecture includes an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {D}}$</tex-math> </inline-formula> adaptor to dynamically adjust the magnitude of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {D}}$</tex-math> </inline-formula> and a control signal generator (CSG) to calibrate the timing of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {D}}$</tex-math> </inline-formula> sourcing. Fabricated in a 40-nm CMOS, the CA-HLDO achieved sub-10-mV voltage droop and 400-ps settling time using a small output capacitor and minimal quiescent current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {Q}}$</tex-math> </inline-formula>). In addition, it provides a power-supply rejection (PSR) more than 10 dB across all frequencies, effectively mitigating PSIJ caused by a noisy and complex PDN.