Analysis of Interface Evolution and Failure Mechanism of Sn _3.5 Ag Microcopper Pillar Solder Joints Under High Current Density

Currently, one of the serious challenges in microelectronic devices is the miniaturization trend of packaging. With the continuous development of micro-electronic packaging towards high density and small size, micro-solder joints will be subjected to thermal-electrical-force and other loads alone or simultaneously under common service conditions, which will cause the failure of the interconnect structure. This study explores interface evolution and failure mechanisms of Sn<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3.5</sub>Ag micro-copper pillar solder joints under high current density. Experiments show that at 3×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> A/cm² and 150°C, cathode-side Ni layers dissolve rapidly, forming intermetallic compounds (IMCs) like Cu<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>Sn and (Cu,Ni)<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub>Sn<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub>, while electromigration-resistant Ag<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>Sn particles aggregate in the solder core to suppress IMC growth. Kirkendall voids nucleate at the Cu-Cu<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub>Sn interface, evolving into cracks under prolonged current stress. ANSYS simulations reveal severe current crowding at copper pillar-trace interfaces, with peak densities reaching 3.82×10⁵ A/cm² . Shorter substrate-side pillars fail earlier due to non-uniform dissolution, while longer chip-side pillars homogenize current flow. Failure modes shift from cathode-side cracking at low densities to pancake-shaped void formation at high densities, guiding microelectronic packaging optimization for high-current reliability.