A Multibit ReRAM Computing-in-Memory Processor With Adaptive Decision Level Nonlinear ADC for Ultra-Low-Energy Keyword Spotting in Mobile Devices

This paper presents an ultra-low-energy keyword spotting (KWS) processor based on the charge-mode multi-level resistive random-access memory (ReRAM) bitcell and adaptive analog-to-digital converter (ADC) quantization. Previous ReRAM computing-in-memory (CIM) architectures have suffered several challenges, including excessive computing energy due to direct current branches, computation non-linearity, and throughput degradation resulting from analog-to-digital conversion. The proposed processor addresses these challenges by introducing a charge-mode multi-bit ReRAM bitcell (CRB), which achieves a 61.39% reduction in multiply-and-accumulate (MAC) energy. The CRB also enhances MAC linearity by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.65\times $</tex-math> </inline-formula>. Additionally, the 5-bit additive powers-of-two ADC achieves a 65.42% reduction in analog-to-digital conversion energy, an 11.70 percentage points decrease in ADC accuracy loss, and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.33\times $</tex-math> </inline-formula> increase in conversion throughput. Furthermore, the pipelined layer fusion clusters reduce intermediate data movement energy to 97.2 nJ and enhance KWS system throughput by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.35\times $</tex-math> </inline-formula>. The proposed processor is designed utilizing 45 nm CMOS technology and compatible ReRAM devices. The processor occupies an area of 0.94 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a 68.5 KB ReRAM cell. The processor also achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.74~\mu $</tex-math> </inline-formula>J/decision energy consumption, 22.59 TOPS/W energy efficiency, and 92.7% accuracy on the Google Speech Commands Dataset.

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Publication Details

Journal
IEEE Transactions on Circuits and Systems I Regular Papers
Published
2025-09-03
DOI
https://doi.org/10.1109/tcsi.2025.3603076
Citations
1
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.73

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article

A Multibit ReRAM Computing-in-Memory Processor With Adaptive Decision Level Nonlinear ADC for Ultra-Low-Energy Keyword Spotting in Mobile Devices

D. Kim, Heein Yoon, Hoichang Jeong, Seungbin Kim et al.
1 citations
IEEE Transactions on Circuits and Systems I Regular Papers
Advanced Memory and Neural Computing
0.73
article

A Multibit ReRAM Computing-in-Memory Processor With Adaptive Decision Level Nonlinear ADC for Ultra-Low-Energy Keyword Spotting in Mobile Devices

D. Kim, Heein Yoon, Hoichang Jeong, Seungbin Kim, Kyuho Lee
article en
1 citations

Abstract

This paper presents an ultra-low-energy keyword spotting (KWS) processor based on the charge-mode multi-level resistive random-access memory (ReRAM) bitcell and adaptive analog-to-digital converter (ADC) quantization. Previous ReRAM computing-in-memory (CIM) architectures have suffered several challenges, including excessive computing energy due to direct current branches, computation non-linearity, and throughput degradation resulting from analog-to-digital conversion. The proposed processor addresses these challenges by introducing a charge-mode multi-bit ReRAM bitcell (CRB), which achieves a 61.39% reduction in multiply-and-accumulate (MAC) energy. The CRB also enhances MAC linearity by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.65\times $</tex-math> </inline-formula>. Additionally, the 5-bit additive powers-of-two ADC achieves a 65.42% reduction in analog-to-digital conversion energy, an 11.70 percentage points decrease in ADC accuracy loss, and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.33\times $</tex-math> </inline-formula> increase in conversion throughput. Furthermore, the pipelined layer fusion clusters reduce intermediate data movement energy to 97.2 nJ and enhance KWS system throughput by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.35\times $</tex-math> </inline-formula>. The proposed processor is designed utilizing 45 nm CMOS technology and compatible ReRAM devices. The processor occupies an area of 0.94 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a 68.5 KB ReRAM cell. The processor also achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.74~\mu $</tex-math> </inline-formula>J/decision energy consumption, 22.59 TOPS/W energy efficiency, and 92.7% accuracy on the Google Speech Commands Dataset.

IEEE Transactions on Circuits and Systems I Regular PapersVol. 73(2)
Yonsei University (KR), Ulsan National Institute of Science and Technology (KR)
National Research Foundation of Korea
Openalex Percentile: Top 24%
Advanced Memory and Neural Computing
0.73
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