A Cross-Cycle Dynamic Active Gate Driver to Minimize Turn-Off Loss With Reduced Spike and <i>dv</i> / <i>dt</i> for SiC MOSFETs

Forsilicon carbide (SiC) MOSFET applications, it has been a constant challenge to address the trade-off among drain-source voltage slew rate (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv</i> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf {ds}}$</tex-math> </inline-formula>/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i>), drain-source voltage spike, and turn-off loss. The existing active gate drivers (AGDs) have not considered the influence of dynamically varying drain current, resulting in increased turn-off loss and voltage spike. To address this issue, this paper proposes a cross-cycle dynamic active gate driver (CDAGD) that features constant (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv</i> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf {ds}}$</tex-math> </inline-formula>/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i>)<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf {max}}$</tex-math> </inline-formula> and spike under dynamic drain current. By deriving the quantitative relationship among the gate current,drain current, (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv</i> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf {ds}}$</tex-math> </inline-formula>/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i>)<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf {max}}$</tex-math> </inline-formula>, and voltage spike, the optimal gate currents in different switching stages are determined. Furthermore, the CDAGD incorporates a cross-cycle gate current regulator (CCGCR) to generate the required gate currents in different stages, and a dynamic switching timing controller (DSTC) to locate the optimal timing of the stages. With the CDAGD providing the optimal gate current, the turn-off loss is minimized with reduced <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv</i> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\mathbf {ds}}$</tex-math> </inline-formula>/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i> and spike.Fabricated in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18\mu $</tex-math> </inline-formula> m BCD process, the CDAGD chip achieves a maximum reduction in turn-off loss of 72.2% and 37.9% compared with the conventional gate driver (CGD) and AGD under varying drain current. A 45.9% reduction in turn-off time is also achieved with the proposed gate driver.