Sequential Logic Optimization using Cycle Time Utilization in Semiconductor Chip Design

Modern semiconductor designs are severely challenged by the uneven distribution of combinational logic from register pairs, forcing an iterative process of timing convergence and poor power-performance-area metrics. This research introduces a framework that captures combinational cell delay as a percentage of a clock cycle utilization across all register-to-register paths in RTL designs. Utilization is calculated path-by-path by combining a three-stage flow for fast compilation, separate calculation of path-by-path utilization, and easy visualization of overall cycle utilization distribution patterns. The flow employs machine learning, combining embedding similarity to match semantically equivalent logic segments, ordering, followed by optimizing register placement while maintaining setup/hold conditions for required flip-flops. The flow can direct engineers with three timing situation categorizations to employ targeted timing solutions that may include collapsing logic segments, vector flop implementation, and/or restructuring the design into a pipeline. Results demonstrate improved timing convergence efforts and inefficient buffering in holding violation corrections. The prescriptive optimization approach allows for the potential to achieve higher frequency operation while speeding design closure. The intention of the implementations is directed towards high-performance computing, including GPU architectures, AI accelerators, and data center processors, which all serve to offer beneficial and predictable workflows for the complex deployment of system-on-chip development.