Statistical measurement technology for capacitance and leakage current characteristics of integrated devices

Abstract This article presents statistical measurement technology capable of measuring the capacitance and leakage current characteristics of integrated devices formed in a 2D array with high speed and precision. The developed array test circuit consists of a platform structure that allows for the formation of various integrated devices as device under test (DUT) using additional processes of sequential integration or 3D chip integration, enabling statistical evaluation of DUTs. To verify its measurement performance, capacitance and gate leakage current were measured for metal-oxide-semiconductor field-effect transistors and metal-insulator-metal capacitors, which were simultaneously formed with the measurement circuits. The developed circuit demonstrated statistical measurement of 5124 cells at a measurement time of 5.9 μs per cell for capacitance and 1.2 ms per cell for current, achieving a measurement precision of 0.04% for fF-order capacitance and 0.57% for fA-order current. Furthermore, the measurement range coverage for capacitance and current was evaluated.