A Three-Segment TDC With a Half-Cycle Single-Stage Vernier Ring for SPAD Sensors

In the readout circuit for single photon avalanche diode (SPAD) sensors, the pixel area poses limitations on using a high-precision time-to-digital converter (TDC) with a complex structure. The gated-ring oscillator (GRO) TDC is usually used in the pixel, but it suffers from timing error in the stabilization time and high power consumption. A three-segment TDC with a half-cycle single-stage Vernier ring is presented in this brief. The ring delay line has no stabilization time. The time resolution of Vernier-ring TDC is not directly related to the oscillation frequency, thus enabling lower power consumption. There is only one stage delay unit in this ring delay line, and its compact area makes it suitable for pixels. A half-cycle Vernier judgment circuit is proposed, which shortens the operating time of the Vernier TDC and reduces its power consumption. An 8×8 SPAD readout integrated circuit (ROIC) was fabricated in a 180-nm CMOS technology. The test results show that the power consumption of the TDC is less than 20 μW at a time resolution of 40 ps, a range of 1 μs, and a frame rate of 10 kHz.